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? semiconductor components industries, llc, 2014 june, 2014 ? rev. 11 1 publication order number: mc10ep446/d mc10ep446, mc100ep446 3.3 v/5 v 8\bit cmos/ecl/ttl data input parallel/serial converter description the mc10/100ep446 is an integrated 8?bit parallel to serial data converter. the device is designed with unique circuit topology to operate for nrz data rates up to 3.2 gb/s. the conversion sequence from parallel data into a serial data stream is from bit d0 to d7. the parallel input pins d0?d7 are configurable to be threshold controlled by cmos, ecl, or ttl level signals. th e serial data rate output can be selected at internal clock data rate or twice the internal clock data rate using the cksel pin. control pins are provided to reset (sync) and disable internal clock circuitry (cken). in either cksel modes, the internal flip?flops are triggered on the rising edge for clk and the multiplexers are switched on the falling edge of clk, therefore, all associated specification limits are referenced to the negative edge of the clock input. additionally, v bb pin is provided for single?ended input condition. the 100 series devices contain temperature compensation network. features ? 3.2 gb/s typical data rate capability ? differential clock and serial outputs ? v bb output for single-ended input applications ? asynchronous data reset (sync) ? pecl mode operating range: v cc = 3.0 v to 5.5 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = ?3.0 v to ?5.5 v ? open input default state ? safety clamp on inputs ? parallel interface can support pecl, ttl or cmos ? these devices are pb?free and are rohs compliant http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 18 of this data sheet. ordering information lqfp?32 fa suffix case 873a marking diagram* *for additional marking information, refer to application note and8002/d. xxx = 10 or 100 a = assembly location wl = wafer lot yy = year ww = work week g or = pb?free package mcxxx ep446 awlyywwg qfn32 mn suffix case 488am 32 1 mcxxx ep446 awlyyww 1 (note: microdot may be in either location)
mc10ep446, mc100ep446 http://onsemi.com 2 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 figure 1. lqfp?32 pinout (top view) warning: all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. d0 d1 d3 d4 d7 v cc s out v ee v bb2 v cc cksel v ef v ee pclk pclk d2 d5 d6 s out v cf sync sync v cc clk clk v bb1 cken cken v ee v cc v cc v cc mc10ep446 mc100ep446 figure 2. qfn?32 pinout (top view) 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 12345678 24 23 22 21 20 19 18 17 exposed pad (ep) d0 d1 d3 d4 d7 v cc cksel d2 d5 d6 clk clk v bb1 cken cken v ee s out v ee pclk pclk s out v cc v cc v cc v cc v ee v bb2 v ef v cf sync sync v cc table 1. pin description pin function d0*?d7* ecl, cmos, or ttl parallel data input s out , s out ecl differential serial data output clk*, clk * ecl differential clock input pclk, pclk ecl differential parallel clock output sync*, sync ** ecl conversion synchronizing differential input (reset)*** cksel* ecl clock input selector cken*, cken * ecl clock enable differential input v cf ecl, cmos, or ttl input selector v ef ecl reference mode connection v bb1 , v bb2 reference voltage output v cc positive supply v ee negative supply * pins will default low when left open. **pins will default high when left open. ***the rising edge of sync will asynchronously reset the internal circuitry. the falling edge of the sync followed by the falling edge of clk initiates the conversion process synchronously on the next rising edge of clk.
mc10ep446, mc100ep446 http://onsemi.com 3 table 2. truth table pin function high low cksel s out : pclk = 8:1 clk: s out = 1:1 s out clk s out : pclk = 8:1 clk: s out = 1:2 s out clk cken synchronously disables normal parallel to serial conversion synchronously enables normal parallel to serial conversion sync asynchronously resets internal flip?flops* synchronous enable *the rising edge of sync will asynchronously reset the internal circuitry. the falling edge of the sync followed by the falling edge of clk initiates the conversion process synchronously on the next rising edge of clk. table 3. input voltage level selection table input function connect to v cf pin ecl mode v ef pin cmos mode no connect ttl mode* 1.5 v 100 mv *for ttl mode, if no external voltage can be provided, the reference voltage can be provided by connecting the appropriate resistor between v cf and v ee pins. table 4. data input operating voltage table power supply (v cc ,v ee ) data inputs (d [0:7]) cmos ttl pecl necl pecl n/a necl n/a n/a n/a power supply resistor value 10% (tolerance) 3.3 v 1.5 k 5.0 v 500
mc10ep446, mc100ep446 http://onsemi.com 4 sync figure 3. logic diagram d0 d q r c dq r c d4 dq r c dq r c dq r c dq r c dq r c dq r c d2 d6 d1 d5 d3 d7 mux 2:1 mux 2:1 mux 2:1 mux 2:1 dq r c dq r c dq r c dq r c 2 mux 2:1 mux 2:1 dq r c dq r c mux 2:1 2 2 dq r c s out s out pclk pclk mux 2:1 cken cken clk clk cksel sync v bb v cf v ef v ee control logic v cc
mc10ep446, mc100ep446 http://onsemi.com 5 table 5. attributes characteristics value internal input pulldown resistor 75 k internal input pullup resistor 37.5 k esd protection human body model machine model charged device model > 2 kv > 100 v > 2 kv moisture sensitivity, indefinite time out of drypack (note 1) pb pkg pb?free pkg lqfp?32 qfn?32 level 2 ? level 2 level 1 flammability rating oxygen index: 28 to 34 ul 94 v?0 @ 0.125 in transistor count 962 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. table 6. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc pecl mode power supply v ee = 0 v 6 v v ee necl mode power supply v cc = 0 v ?6 v v i pecl mode input voltage necl mode input voltage v ee = 0 v v cc = 0 v v i v cc v i v ee 6 ?6 v i out output current continuous surge 50 100 ma i bb v bb sink/source 0.5 ma t a operating temperature range ?40 to +85 c t stg storage temperature range ?65 to +150 c ja thermal resistance (junction?to?ambient) 0 lfpm 500 lfpm lqfp?32 lqfp?32 80 55 c/w jc thermal resistance (junction?to?case) standard board lqfp?32 12 to 17 c/w ja thermal resistance (junction?to?ambient) 0 lfpm 500 lfpm qfn?32 qfn?32 31 27 c/w jc thermal resistance (junction?to?case) 2s2p qfn?32 12 c/w t sol wave solder pb?free <2 to 3 sec @ 260 c 265 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected.
mc10ep446, mc100ep446 http://onsemi.com 6 table 7. 10ep dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 2) symbo l characteristic ?40 c 25 c 85 c uni t min typ max min typ max min typ max i ee power supply current 90 110 140 90 110 140 95 115 145 ma v oh output high voltage (note 3) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mv v ol output low voltage (note 3) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mv v ih input high voltage (single?ended) cmos pecl ttl 2000 2090 2000 3300 3300 3300 2000 2155 2000 3300 3300 3300 2000 2215 2000 3300 3300 3300 mv v il input low voltage (single?ended) cmos pecl ttl 0 1365 0 800 1690 800 0 1460 0 800 1755 800 0 1490 0 800 1815 800 mv v bb output voltage reference 1790 1840 1990 1855 1905 2055 1915 1965 2115 mv v ihcmr input high voltage common mode range (dif- ferential configuration) (note 4) 2.0 3.3 2.0 3.3 2.0 3.3 v i ih input high current 150 150 150 a i il input low current (all except sync, sync ) sync, sync 0.5 ?150 0.5 0.5 ?150 0.5 0.5 ?150 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to ?2.2 v. 3. all loading with 50 to v cc ? 2.0 v. 4. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep446, mc100ep446 http://onsemi.com 7 table 8. 10ep dc characteristics, pecl v cc = 5.0 v, v ee = 0 v (note 5) symbo l characteristic ?40 c 25 c 85 c uni t min typ max min typ max min typ max i ee power supply current 90 110 140 90 110 140 95 115 145 ma v oh output high voltage (note 6) 3865 3950 4115 3930 4055 4180 3990 4115 4240 mv v ol output low voltage (note 6) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mv v ih input high voltage (single?ended) cmos pecl ttl 3500 3790 2000 5000 5000 5000 3500 3855 2000 5000 5000 5000 3500 3915 2000 5000 5000 5000 mv v il input low voltage (single?ended) cmos pecl ttl 0 3065 0 1500 3390 800 0 3130 0 1500 3455 800 0 3190 0 1500 3915 800 mv v bb output voltage reference 3490 3540 3690 3555 3605 3755 3615 3665 3815 mv v ihcmr input high voltage common mode range (dif- ferential configuration) (note 7) 2.0 5.0 2.0 5.0 2.0 5.0 v i ih input high current 150 150 150 a i il input low current (all except sync, sync ) sync, sync 0.5 ?150 0.5 0.5 ?150 0.5 0.5 ?150 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. input and output parameters vary 1:1 with v cc . v ee can vary +2.0 v to ?0.5 v. 6. all loading with 50 to v cc ? 2.0 v. 7. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep446, mc100ep446 http://onsemi.com 8 table 9. 10ep dc characteristics, necl v cc = 0 v, v ee = ?5.5 v to ?3.0 v (note 8) symbo l characteristic ?40 c 25 c 85 c uni t min typ max min typ max min typ max i ee power supply current 90 110 140 90 110 140 95 115 145 ma v oh output high voltage (note 9) ?1135 ?1010 ?885 ?1070 ?945 ?820 ?1010 ?885 ?760 mv v ol output low voltage (note 9) ?1935 ?1810 ?1685 ?1870 ?1745 ?1620 ?1810 ?1685 ?1560 mv v ih input high voltage (single?ended) ?1210 ?885 ?1145 ?820 ?1085 ?760 mv v il input low voltage (single?ended) ?1935 ?1610 ?1870 ?1545 ?1810 ?1485 mv v bb output voltage reference ?1510 ?1460 ?1310 ?1445 ?1395 ?1245 ?1385 ?1335 ?1185 mv v ihcmr input high voltage common mode range (differential configuration) (note 10) v ee +2.0 0.0 v ee +2.0 0.0 v ee +2.0 0.0 v i ih input high current 150 150 150 a i il input low current (all except sync, sync ) sync, sync 0.5 ?150 0.5 0.5 ?150 0.5 0.5 ?150 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. input and output parameters vary 1:1 with v cc . 9. all loading with 50 to v cc ? 2.0 v. 10. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. table 10. 100ep dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 11) symbo l characteristic ?40 c 25 c 85 c uni t min typ max min typ max min typ max i ee power supply current 90 110 130 90 110 130 95 115 135 ma v oh output high voltage (note 12) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv v ol output low voltage (note 12) 1305 1480 1605 1305 1480 1605 1305 1480 1605 mv v ih input high voltage (single?ended) cmos pecl ttl 2000 2075 2000 3300 3300 3300 2000 2075 2000 3300 3300 3300 2000 2075 2000 3300 3300 3300 mv v il input low voltage (single?ended) cmos pecl ttl 0 1305 0 800 1675 800 0 1305 0 800 1675 800 0 1305 0 800 1675 800 mv v bb output voltage reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 mv v ihcmr input high voltage common mode range (differential configuration) (note 13) 2.0 3.3 2.0 3.3 2.0 3.3 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to ?2.2 v. 12. all loading with 50 to v cc ? 2.0 v. 13. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep446, mc100ep446 http://onsemi.com 9 table 11. 100ep dc characteristics, pecl v cc = 5.0 v, v ee = 0 v (note 14) symbo l characteristic ?40 c 25 c 85 c uni t min typ max min typ max min typ max i ee power supply current 90 110 130 90 110 130 95 115 135 ma v oh output high voltage (note 15) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mv v ol output low voltage (note 15) 3005 3180 3305 3005 3180 3305 3005 3180 3305 mv v ih input high voltage (single?ended) cmos pecl ttl 3500 3775 2000 5000 5000 5000 3500 3775 2000 5000 5000 5000 3500 3775 2000 5000 5000 5000 mv v il input low voltage (single?ended) cmos pecl ttl 0 3005 0 1500 3375 800 0 3005 0 1500 3375 800 0 3005 0 1500 3375 800 mv v bb output voltage reference 3475 3575 3675 3475 3575 3675 3475 3575 3675 mv v ihcmr input high voltage common mode range (differential configuration) (note 16) 2.0 5.0 2.0 5.0 2.0 5.0 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. input and output parameters vary 1:1 with v cc . v ee can vary +2.0 v to ?0.5 v. 15. all loading with 50 to v cc ? 2.0 v. 16. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. table 12. 100ep dc characteristics, necl v cc = 0 v, v ee = ?5.5 v to ?3.0 v (note 17) symbo l characteristic ?40 c 25 c 85 c uni t min typ max min typ max min typ max i ee power supply current 90 110 130 90 110 130 95 115 135 ma v oh output high voltage (note 18) ?1145 ?1020 ?895 ?1145 ?1020 ?895 ?1145 ?1020 ?895 mv v ol output low voltage (note 18) ?1995 ?1820 ?1695 ?1995 ?1820 ?1695 ?1995 ?1820 ?1695 mv v ih input high voltage (single?ended) ?1225 ?880 ?1225 ?880 ?1225 ?880 mv v il input low voltage (single?ended) ?1995 ?1625 ?1995 ?1625 ?1995 ?1625 mv v bb output voltage reference ?1525 ?1425 ?1325 ?1525 ?1425 ?1325 ?1525 ?1425 ?1325 mv v ihcmr input high voltage common mode range (differential configuration) (note 19) v ee +2.0 0.0 v ee +2.0 0.0 v ee +2.0 0.0 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 17. input and output parameters vary 1:1 with v cc . 18. all loading with 50 to v cc ? 2.0 v. 19. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep446, mc100ep446 http://onsemi.com 10 table 13. ac characteristics v cc = 0 v; v ee = ?3.0 v to ?5.5 v or v cc = 3.0 v to 5.5 v; v ee = 0 v (note 20) symbol characteristic ?40 c 25 c 85 c unit min typ max min typ max min typ max f max maximum frequency (figure 15) cksel high cksel low 3.2 1.6 3.4 1.7 3.2 1.6 3.4 1.7 3.2 1.6 3.4 1.7 ghz t plh , t phl propagation delay to output differential cksel = 0 clk to s out , clk to pclk 650 700 750 800 850 900 700 750 800 850 900 950 725 775 850 900 975 1025 ps cksel = 1 clk to s out , clk to pclk 775 850 875 950 975 1050 825 900 925 1000 1025 1100 875 950 1000 1075 1125 1200 ps t s setup time d to clk+ (figure 4) sync? to clk? (figure 5) cken+ to clk? (figure 6) ?375 200 70 ?425 140 40 ?400 200 70 ?450 140 40 ?450 200 70 ?500 140 40 ps t h hold time d to clk+ (figure 4) sync? to clk? clk? to cken? (figure 6) ?525 0 75 ?575 45 ?550 0 75 ?600 45 ?600 0 75 ?650 45 ps t pw minimum pulse width (note 22) data (d0?d7) sync cken 150 200 145 150 200 145 150 200 145 ps t jitter random clock jitter (rms) f max typ 0.2 < 1 0.2 < 1 0.2 < 1 ps v pp input differential voltage swing (note 21) 150 800 1200 150 800 1200 150 800 1200 mv t r t f output rise/fall times s out (20% ? 80%) 50 100 150 70 120 170 90 140 190 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 20. measured using a 750 mv source, 50% duty cycle clock source. all loading with 50 to v cc ? 2.0 v. 21. v pp (min) is the minimum input swing for which ac parameters are guaranteed. 22. the minimum pulse width is valid only if the setup and hold times are respected.
mc10ep446, mc100ep446 http://onsemi.com 11 clk sync sync t s clk t s clk t h cken figure 4. setup and hold time for data t h t s data setup time + 0 ? clk figure 5. setup time for sync figure 6. setup and hold time for cken data valid
mc10ep446, mc100ep446 http://onsemi.com 12 application information the mc10/100ep446 is an integrated 8:1 parallel to serial converter. an attribute for ep446 is that the parallel inputs d0?d7 (pins 17 ? 24) can be configured to accept either cmos, ecl, or ttl level signals by a combination of interconnects between v ef (pin 27) and v cf (pin 26) pins. for cmos input levels, leave v ef and v cf open. for ecl operation, short v cf and v ef (pins 26 and 27). for ttl operation, connect a 1.5 v supply reference to v cf and leave the v ef pin open. the 1.5 v reference voltage to v cf pin can be accomplished by placing a 1.5 k or 500 between v cf and v ee for 3.3 v or 5.0 v power supplies, respectively. note: all pins requiring ecl voltage inputs must have a 50 terminating resistor to v tt (v tt = v cc ? 2.0 v). the cksel input (pin 2) is provided to enable the user to select the serial data rate output between internal clock data rate or twice the internal clock data rate. for cksel low operation, the time from when the parallel data is latched to when the data is seen on the s out is on the falling edge of the 7 th clock cycle plus internal propagation delay (figure 7). note the pclk switches on the falling edge of clk. figure 7. timing diagram 1:8 parallel to serial conversion with cksel low clk sout pclk d0 d0?2 d1 d2 d3 d4 d5 d6 d7 d2?2 d3?2 d4?2 d5?2 d6?2 d7?2 d0?3 d1?3 d2?3 d3?3 d4?3 d5?3 d6?3 d7?3 d1?2 cksel d0?1 d1?1 d2?1 d3?1 d4?1 d5?1 d6?1 d7?1 d0?2 d1?2 d2?2 d3?2 d6?2 d0?1 d2?1 d3?1 d4?1 d5?1 d6?1 d7?1 d1?1 d5?2 d0?4 d1?4 d2?4 d3?4 d4?4 d5?4 d6?4 d7?4 1234567 number of clock cycles from data latch to sout data latched data latched data latched data latched d4?2
mc10ep446, mc100ep446 http://onsemi.com 13 similarly, for cksel high operation, the time from when the parallel data is latched to when the data is seen on the s out is on the rising edge of the 14 th clock cycle plus internal propagation delay (figure 8). furthermore, the pclk switches on the rising edge of clk. data latched data latched data latched figure 8. timing diagram 1:8 parallel to serial conversion with cksel high clk sout pclk d0 d0?1 d1 d2 d3 d4 d5 d6 d7 d2?1 d3?1 d4?1 d5?1 d6?1 d7?1 d1?1 cksel d0?2 d1?2 d2?2 d3?2 d4?2 d5?2 d6?2 d7?2 d0?3 d1?3 d2?3 d3?3 d4?3 d5?3 d6?3 d7?3 d0?1 d1?1 d2?1 d3?1 d4?1 d5?1 d6?1 d7?1 d0?2 d1?2 12345678910 121314 11 number of clock cycles from data latch to sout
mc10ep446, mc100ep446 http://onsemi.com 14 the device also features a differential sync input (pins 29 and 30), which asynchronously reset all internal flip?flops and clock circuitry on the rising edge of sync. the release of sync is a synchronous process, which ensures that no runt serial data bits are generated. the falling edge of the sync followed by a falling edge of clk initiates the start of the conversion process on the next rising edge of clk (figures 9 and 10). as shown in the figures below, the device will start to latch the parallel input data a fter the a falling edge of sync , followed by the falling edge clk , on the next rising of edge of clk for cksel low figure 9. timing diagram 1:8 parallel to serial conversion with cksel low and sync clk sync sout pclk d0 d0?2 d1 d2 d3 d4 d5 d6 d7 d2?2 d3?2 d4?2 d5?2 d6?2 d7?2 d0?3 d1?3 d2?3 d3?3 d4?3 d5?3 d6?3 d7?3 d1?2 cksel d0?1 d1?1 d2?1 d3?1 d4?1 d5?1 d6?1 d7?1 d0?2 d1?2 d2?2 d3?2 d4?2 d6?2 d0?1 d2?1 d3?1 d4?1 d5?1 d6?1 d7?1 d1?1 d5?2 d0?4 d1?4 d2?4 d3?4 d4?4 d5?4 d6?4 d7?4 1234567 data latched data latched data latched data latched figure 10. synchronous release of sync for cksel low clk sync sync (asynchronous reset) sync (synchronous enable) number of clock cycles from data latch to sout
mc10ep446, mc100ep446 http://onsemi.com 15 for cksel high, as shown in the timing diagrams below, the device will start to latch the parallel input data after the falling edge of sync , followed by the falling edge clk , on the second rising edge of clk (figures 11 and 12). figure 11. timing diagram 1:8 parallel to serial conversion with cksel high and sync clk sync sout pclk d0 d0?1 d1 d2 d3 d4 d5 d6 d7 d2?1 d3?1 d4?1 d5?1 d6?1 d7?1 d1?1 c ksel d0?2 d1?2 d2?2 d3?2 d4?2 d5?2 d6?2 d7?2 d0?3 d1?3 d2?3 d3?3 d4?3 d5?3 d6?3 d7?3 d0?4 d1?4 d2?4 d3?4 d4?4 d5?4 d6?4 d7?4 d0?1 d1?1 d2?1 d3?1 d4?1 d5?1 d6?1 d7?1 d0?2 d1?2 1234567 data latched 8 9 10 12 13 14 11 data latched data latched figure 12. synchronous release of sync for cksel high clk sync sync (asynchronous reset) sync (synchronous enable) number of clock cycles from data latch to sout
mc10ep446, mc100ep446 http://onsemi.com 16 the differential synchronous cken inputs (pins 6 and 7), disable the internal clock circuitry. the synchronous cken will suspend all of the device activities and prevent runt pulses from being generated. the rising edge of cken followed by the falling edge of clk will suspend all activities. the falling edge of cken followed by the falling edge of clk will resume all activities (figure 13). figure 13. timing diagram with cken with cksel high clk cken sout cksel d1?1 d0?1 d2?1 d3?1 pclk d4?1 d5?1 internal clock disabled internal clock enabled the differential pclk output (pins 14 and 15) is a word framer and can help the user synchronize the serial data output, s out (pins 11 and 12), in their applications. furthermore, pclk can be used as a trigger for input parallel data (figure 14). an internally generated voltage supply, the v bb pin, is available to this device only. for single?ended input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb should be left open. also, both outputs of the differential pair must be terminated (50 to v tt ) even if only one output is used. figure 14. pclk as trigger application trigger pattern generator data format logic (fpga, asic) parallel data output clk pclk ep446 parallel data input sync s out serial data clk reset
mc10ep446, mc100ep446 http://onsemi.com 17 0 100 200 300 400 500 600 700 800 0 500 1000 1500 2000 2500 3000 3500 figure 15. typical v outpp versus input clock frequency, 25 c input clock frequency (mhz) v outpp (mv) cksel low cksel high figure 16. sout system jitter measurement (condition: 3.4 ghz input frequency, cksel high, beofe32 bit pattern on sout
mc10ep446, mc100ep446 http://onsemi.com 18 figure 17. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 2.0 v ordering information device package shipping ? mc10ep446fag lqfp?32 (pb?free) 250 units / tray mc10ep446far2g 2000 / tape & reel mc10ep446mng qfn?32 (pb?free) 74 units / rail mc100ep446mng 74 units / rail MC100EP446FAG lqfp?32 (pb?free) 250 units / tray mc100ep446far2g 2000 / tape & reel mc10ep446mnr4g qfn?32 (pb?free) 1000 / tape & reel mc100ep446mnr4g 1000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. resource reference of application notes an1405/d ? ecl clock distribution techniques an1406/d ? designing with pecl (ecl at +5.0 v) an1503/d ? eclinps i/o spice modeling kit an1504/d ? metastability and the eclinps family an1568/d ? interfacing between lvds and ecl an1672/d ? the ecl translator guide and8001/d ? odd number counters design and8002/d ? marking and date codes and8020/d ? termination of ecl logic devices and8066/d ? interfacing with eclinps and8090/d ? ac characteristics of ecl devices
mc10ep446, mc100ep446 http://onsemi.com 19 package dimensions 1 8 9 17 25 32 ae ae p detail y base n j d f metal section ae?ae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad detail ad a1 b1 v1 4x s 4x 9 ?t? ?z? ?u? t-u 0.20 (0.008) z ac t-u 0.20 (0.008) z ab 0.10 (0.004) ac ?ac? ?ab? m 8x ?t?, ?u?, ?z? t-u m 0.20 (0.008) z ac 32 lead lqfp case 873a?02 issue c notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?ab? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?t?, ?u?, and ?z? to be determined at datum plane ?ab?. 5. dimensions s and v to be determined at seating plane ?ac?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?ab?. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.450 0.750 0.018 0.030 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref
mc10ep446, mc100ep446 http://onsemi.com 20 package dimensions qfn32 5x5, 0.5p case 488am issue a seating note 4 k 0.15 c (a3) a a1 d2 b 1 9 17 32 e2 32x 8 l 32x bottom view top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. plane *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 3.35 0.30 3.35 32x 0.63 32x 5.30 5.30 l1 detail a l alternate terminal constructions l ??? ??? 0.80 a1 ??? a3 0.20 ref b 0.18 d 5.00 bsc d2 2.95 e 5.00 bsc 2.95 e2 e 0.50 bsc 0.30 l k 0.20 1.00 0.05 0.30 3.25 3.25 0.50 ??? max ??? l1 0.15 e/2 note 3 pitch dimension: millimeters recommended a m 0.10 b c m 0.05 c on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc10ep446/d eclinps is a trademark of semiconductor components industries, llc (scillc) literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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